CTS HCSL输出时钟振荡器，灵活性与多元化兼并的CTS公司，凭借着自身的聪明才智，开发大量高质量的晶振产品，同时也拥有快速交付的能力，以及对于产品超强的灵活性，能够以高于用户满意度为最大的标准，致力于为用户提供高质量低损耗的时钟振荡器产品为主，高速电流导引逻辑[HCSL]输出为 在外围组件互连Express中找到 [PCIe]应用，英特尔和英伟达芯片组 其他人。HCSL是一个差分输出标准，类似 至LVPECL，提供高阻抗输出 快速切换时间。其他优势包括与LVDS和相比的平均功耗 LVPECL和低相位抖动性能。

High Speed Current Steering Logic [HCSL] outputs are found in Peripheral Component Interconnect Express [PCIe] applications, Intel and Nvidia chipsets among others. HCSL is a differential output standard, similar to LVPECL, providing a high impedance output with fast switching times. Other advantages include average power consumption when compared to LVDS and LVPECL and low phase jitter performance.

差分输出有一个15mA电流源，来自开射极或源极，漏极未端接，需要外部50欧姆电阻接地。如果需要，10至30欧姆系列 可以增加电阻来减少过冲或振铃 波形。参见图1和图2。

PCIe是由PCI特别兴趣组[PCI SIG]开发的串行点对点互连标准，最初用于 帮助计算机制造商实施英特尔规范。然而，由于其低成本和高数据吞吐量，PCIe一直是在多个应用标准中采用包括刀片服务器、数据存储 [SATAe & M.2]，嵌入式计算， 3D图形、网络[千兆以太网]和通信平台。在 鉴于其普及性、简单性和可扩展性；PCIe电气接口正用于ASICs、FPGAs和SOC。这为设计师提供灵活的有源晶振解决方案在他们的系统中进行高速数据传输。CTS HCSL输出时钟振荡器

PCIe is a serial point-to-point interconnect standard developed by the PCI Special Interest Group [PCI SIG], originally for the PC market to help computer manufacturers implement the Intel specification. However, due to its low cost and high data throughput, PCIe has been adopted in several application standards including blade servers, data storage [SATAe & M.2], embedded computing, 3D graphics, networking [Gigabit Ethernet], and communication platforms. In view of its popularity, simplicity and scalability; the PCIe electrical interface is being used in ASICs, FPGAs and SoCs. This provides designers with flexible solutions for high speed data transfer in their systems.

基本的PCIe体系结构由两台设备之间的数据链路组成，这两台设备可以有1到32条通道。 通道被区分为x1、x2、x4、x8、x12、x16和x32 PCIe链路。每个通道由以下内容定义 差分线对，一对用于发送[Tx],另一对用于接收[Rx]数据。A 单个通道将以每周期1位的速率传输数据，因此增加更多的通道将增加 传输速率。参见图3和图4。

The basic PCIe architecture consists of a data link between two devices that can have 1 to 32 lanes. The lanes are differentiated as x1, x2, x4, x8, x12, x16 and x32 PCIe links. Each lane is defined by differential pair of wires, one pair for transmitting [Tx] and the other pair for receiving [Rx] data. A single lane will carry data at a rate of 1 bit per cycle, therefore adding more lanes will increase the transfer rate. See figures 3 and 4.CTS HCSL输出时钟振荡器

An external reference clock is required to transmit the data. The standard clock requirements include a frequency of 100MHz, stability ±300ppm maximum and HCSL output. Although the reference clock frequency has remained the same for all PCIe generations, from PCIe1.0 to PCIe4.0, the jitter requirements have improved to support the higher transfer rates in succeeding versions. A history of PCIe clock jitter requirements are outlined in table Table 1, as well as highlighting the new Gen5.0 standard that is developing in 2019. 

参考时钟的抖动会直接影响器件之间的数据传输效率。改进 抖动性能有助于消除数据传输中的延迟 给设计师以灵活性。

PCIe标准是多种应用标准中用于互连外围设备的核心技术。随着PCIe 5.0的开发，它将使400GE得以大规模采用 技术，因为其16通道系统的全双工带宽约为128GB/s。这 将成为支持响应时间和高性能的下一代技术的关键 5G和物联网的带宽需求。